November 2nd, 2009

Trajedy... for YOUUUUUUUUUUUU!!!!

US Continues Quagmire Building Efforts in Afghanistan


According to sources at the Pentagon, American quagmire-building efforts continued apace in Afghanistan this week, as the geographically rugged, politically unstable region remained ungovernable, death tolls continued to rise, and the grim military campaign persisted as hopelessly as ever.

In fact, many government officials now believe that the United States and its allies could be as little as six months away from their ultimate goal: the total quagmirification of Afghanistan.


http://www.theonion.com/content/news/u_s_continues_quagmire_building
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Tilera's 100 core chip - highly advanced interconnect and routing.


While the cores might not be overly complex, the on-chip busses are. Each Gx core has 64K of L1 cache, 32K data and 32K instruction, along with a unified 8-way 256KB L2 cache. The cache is totally non-blocking, completely coherent, and the cache subsystem can reorder requests to other caches or DRAM. On top of this, the core supports cache pinning to keep often used data or instructions in cache. On the 100 core model, the Gx has 32MB of cache.

Tiles are the name Tilera uses for for a basic unit of repetition. The 16 core Gx has 16 tiles, the 64 core Gx has 64, etc. A tile consists of a core, the L1 and L2 caches, and something Tilera calls the Terabit Switch. More than anything, this switch is the heart of the chip.

Remember when we said that cramming 100 cores on a die is not a big problem, but feeding them is? The Terabit Switch is how Tilera solves the problem, and it is a rather unique solution. Instead of one off-core bus, there are five. Each of them has a dedicated purpose, and that not only gives huge bandwidth, it also goes a fair way towards minimizing contention. Cache traffic will never be stepped on by user data, and so on.

The five networks are called QDN, RDN, FDN, IDN and UDN. In the last two generations of Tilera chips, all of these networks were 32 bits wide, but on the Gx, the widths vary to give each one more or less bandwidth depending on their functions.


http://www.semiaccurate.com/2009/10/29/look-100-core-tilera-gx/